Ternary comparator



April 21, 1970 NH. HANSON 3,508,199*

' TERNARICOMPARATOR original Filed sept. 30,' 1965 l ELEMENT ELEMENT q+| 3 L9 ELEMENT A2q l INVENTOR WILL/AM H. -/A/VSU/V wwf@ ATTORNEY United States Patent O U.S. Cl. S40-146.2 4 Claims ABSTRACT OF THE DISCLOSURE A ternary comparator utilizing multi-input ternary threshold logic elements for performing ternary arithmetical operations.

This is a divisional application of the commonly assigned copending application of W. H. Hanson, Ser. No. 491,594, led Sept. 30, 1965 and entitled Signed Ternary Carry Generator.

Both the conventional and signed ternary number systems, along with associated arithmetical operations, are defined and discussed in Patent No. 3,210,529 issued Oct. 5, 1965 to W. H. Hanson and assigned to the assignee of the present invention.

Conventional ternary comparator networks are generally serial in nature and consist of a serial arrangement of ternary comparator stages such as those disclosed in a paper by W. H. Hanson entitled Ternary Threshold Logic, published in IEEE Transactions on Electronic Computers, vol IEC-12, pp. 191-197, lune 1963. Serial networks of this type require a relatively large number of elements and logic levels to effect. Some further properties of ternary threshold logic are discussed in a note by R. Merrill entitled Some Properties of Ternary Threshold Logic published in IEEE Transaction on Electronic Computers, vol. IEC-13, pp. 632-635, October 1964.

It has been determined that a comparison, through the jqth digit-order, of two ternary words of the form n...Ak...AlandB... Bk...B1isrepre sented 'by the logical function,

It is proposed by this invention to reduce the number of elements and logic levels necessary to generate signals representative of signed ternary comparisons by utilizing these determinations and their logical equivalents.

The invention is effected by employing multi-input ternary threshold logic elements. There are a variety of circuits available, capable of performing the logical threshold function, which are well known in the art (such as described by R. Schauer et al. in Some Applications of Magnetic Film Paramatrons As Logical Devices IRE, Transactions on Electronic Computers, vol. EC-9, pp. 315-320, September 1960) and these circuits, of themselves, do not constitute a part of this invention.

The output, Y, of a ternary threshold logic element having n inputs X11 Xk X1 with associated weights wn wk w1, where wkl, and threshold t, where X1 15:52 wk can be represented as follows:

Y=WnXnt tWkXkt twlXl 3,508,199 Patented Apr. 21, 1970 The value of the ternary threshold logic function, Y is n determined as follows:

In the signed ternary number system;

Y=0 in all other cases, where Xk=+1, 0, 1, and in the conventional ternary number system;

Y=1 in all other cases, where Xk=2, 1, 0.

It Will thus be seen that by implementing the determinations set forth above with multi-input ternary threshodl logic elements, a comparison of two ternary words can be realized in a relatively short period of time utilizing a relatively small number of elements. The novel features which are considered characteristics of this invention are set forth with particularity in the appended claims. The invention itself, lboth as to its organization and method lof operation, as well as additional advantages thereof, will be best understood from the following description when read in connection with the accompanying drawings, in which:

The ligure is a logical block diagram of a preferred embodiment of a comparator designed in accordance with this invention.

The drawing generally shows block diagrams of a basic comparator designed in accordance with the present invention. In the figure each of the blocks represent a multi-input ternary threshold logic element. The term appearing Within each of the blocks represents the threshhold of the element. The term `appearing at each input to each of the elements represents the weight accorded the associated input.

With reference now to the ligure, a logical block diagram of a comparator according to the present invention is shown. The comparator, for generating a signal, Kn, representative of a comparison of two ternary words of theformAn. Ak.. A1andBn. Bk. B1, comprises m multi-input ternary threshold logic elements arranged in m logic levels. The number of elements, m necessary to generate Kn is given by, n/q where:

n/ q =n/ q, if the quotient is an integer,

:n/ q rounded up to the next higher integer, if the quotient is not an integer, q=p1)/2, `and p is the number of distinct input signals allowed per element.

Each of the elements, j=1 m-l, receives 2q signal representations of digit-orders Aqj ANAH, and 'qj q(j 1)+1, of the words to be compared, A and B, and a signal representation of Kq 1), the signal generated 'by the next lower order element. Each of these elements generates a signale Kqj, representative of a comparison through the qi digit order. The mth element receives 2r signal representations of digit-orders An An ,+1 and En '15,14% of words to be compared, A and B, and a signal representation of K the signal generated by the (mf-DH1 element, where r is the non-zero remainder of n/q. If the remainder of n/ q is zero then r=q. The mth element generates a signal representative ofKn.

Each of the elements j=l 111-1 has a threshold element) is determined by the specic type of hardware Of t(t=l and is coupled so as to receive Zq-i-l utilized to implement the invention. The factor t, which is input signals representative of digit-orders utilized in determining the threshold of the various elements is preferably one; however any other integral value will render the invention operative.

What is claimed is:

1. A ternary comparator for generating a signal Kn, representive of a comparison of two words of the form Ak .A1 and En k El, compris- En q(j 1)+1, and Kq(j 1), the latter being representative of the signal generated by the next lower order element. Each of said digit-order inputs is weighted by a factor 2W1=(2t)(31-l) and Kq(j 1) is weighted by a An factor ofvwl. The ith element utilizes said digit-order and 1 ing; Comparison Signals t generate a Signal in aCCOrdaDC@ m multi-input ternary threshold logic elements for gen- With the logical fllIlCtOIl erating a signal representation Kn, each of said signal generating elements j=1 M: 1, coupled to K =2w A1210 F1 t2in-A 92u13 n q q, q q, t i qo iwft no 1 +1K the next lowerY signal generating element for generat- 2w1AUr1 +1 2w1BQG-DHt 1G-1) 15 ing a signal representative of, Knj, a comparison where j=1 m-l and for each j, =l q through qjth digit-order of An Ak A1 and The mth element hasathreshold of tandis coupled so as Bn Bk B1, comprising:

to receive Zr-I-l input signals representative of digit-orders input means for receiving signal representations of An An n+1, l-n 3n ,+1, and Kn r, the latter digit orders Aq] Aq(j 1)+1,

being representative of the signal generated by the (m1)th element. Each of said digit-order inputs is BCM-DH and Kq-D and Weighted by a factor 2w1=(2t)3i*1 and K r is weighted by a factor of w1. The mth element utilizes said digit-order and comparison signals to generate a signal in accorda multi-input ternary threshold logic element coupled to said input means for utilizing said digitorder and comparison signals to generate Kqj in ance Wlth the logical funcuon: accordance with the logical function,

@w1 Arr +1 tgwlfrr +1115 Kn" tZwiAqo-i +it2l0iJ5'q(s-n+itKqti-i) said signal generating element, y`=m coupled to the next lower signal generating element for generating a signal representative of Kn, comprising:

input means for receiving signal representations of where;z'=1 r.

Control signal, K0, an input to the rst element, determines what condition Kn will detect, in accordance with thefouowmg digirordersan Anmnnl,

Knml implies AZB Bn Brum-n+1 and Kqtm-i), Kn=l implies A B and K0:0 a multi-input ternary threshold logic element coupled to said input means for utilizing said digit- 40 order and comparison signals to generate Kn in -accordance with the logical function Kn`=1 implies A B Kn:2wr1nt2wr-n* 2w1An(,n n+iUIMm-DHKQm-n Kn=1 implies 142B 2. A comparator as dened in claim 1 in which each of aid multi-input ternary threshold logic elements is a Following are two illustrative examples of specific ternary s. comparators designed in accordance with this invention. Slgped ternary threshold loglc e1ement sald elments Let 5 t 1 and 30 Then (1 2 m 15 2 being arranged such the comparison signal Kn is genand Zwp) 61:1) erated in m logic levels.

1 3. A comparator as defined in claim 2 in which m is With these arameters iven the s ecific com arator is defined by thelfoiiowing ioggicai functims p defmed by th? .funcion ?/q q=(p1)/ 2 l s the First Element K 6A 16E 12A 12F 1K" 50 number of distinct input signals per threshold element,

2 2 2 l l n andris the non-zero remainder of n/q. Second Element: K4=6AI4I4ZA323K2 4. A signal generating element for generating a signal Thlfd Element- K6=6As 6136 21145 Bs {(4 Kqj, representative of a comparison through the qfh digit- Fourh ElementakK--AIB is 2A? 237 6 order of two ternary words o the form An Ak 55 A1, and Bn Bk B1, comprising:

input means for receiving signal represent ations of digit- 0I`deIS Aqj Aq(j 1), Bqj Bq(j 1)+1 and Fourteenth Element: X28:6/12816F2812A2712F271K26 Fifteenth Element: K30=6A3016'3012A2912291K23 Let 11:7, 1:1, and 11:29. Then q=3, 11:10, r=2, 6o and 2w1=(2) (31*1). With these parameters given the specic comparator isdened by the following logical functions.

First Element: K3: 18A 3118'E316A 216F212A112F11K0 SeCOIld Elementi K6: 6118-516A516F512A412F41K3 :i1 i :k di k ith Element:

1 n=isAn11snneA3garenne/133 212F3k2113(1 1) s i 1 d# =l Ninth Element:

Kzv=18A 27118F2716A 261632612/1 251217251K24 Tenth. Element: X29:6A2g162912142312g2311 27 The number of distinct input signals allowed per elecomparison signal Kum- 1), the latter being representative of the comparison signal generated by a next lower element, and

multi-input ternary threshold logic element coupled to said input means for utilizing said digit-order and comparison signals to generate a signal representative of Kqj in accordance with the logical function,

References Cited UNITED STATES PATENTS l/1967 Bailey S40-146.2 2/1967 Nelson 340--l46.2

EUGENE G. BOTZ, Primary Examiner ment, p (or the total number of input signals allowed per R. S. DILDINE, JR., Assistant Examiner UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 5,508,199 Apri1 21, 1970 William H. Hanson It is certified that error appears in the above identified patent and that said Letters Patent are hereby corrected as shown below:

Column 4, line 13, .M=l" should read -l- .M-l line Il IY .A i O 57, after orders insert AqJ q(J l)+1'Bq] Bq(] l)+l Signed and sealed this 22nd day of December 1970.

(SEAL) Attest:

WILLIAM E. SCHUYLER, JR.

Commissioner of Patents Edward M. Fletcher, Jr.

Attesting Officer 

